Cyclone IV GX CPRI IP Cores at Data Rates Above 0.6144 Gbps Have Wrong TX Transceiver Clock Connection

In CPRI IP core variations that target a Cyclone IV GX device and that run at a CPRI line rate of 1.2288, 2.4576, or 3.072 Gbps, the TX transmitter reference clock input signal is connected incorrectly internally.

To work around this issue, edit the <instance>/altera_cpri.vhd file to replace the text

pll_inclk(0) => gxbref_clk

with the replacement text

pll_inclk(0) => gxb_pll_inclk

in the following VHDL component instances:

inst_cyclone4gx_1228_s_tx

inst_cyclone4gx_2457_s_tx

inst_cyclone4gx_3072_s_tx

This issue is fixed in version 13.1 of the CPRI MegaCore function.