The User Guide for the Device-Specific Power Delivery Network (PDN) Tool (PDF) describes how to derive decoupling in power supply sharing scenarios. However, this is with respect to sharing multiple power pins such as VCCIO, VCCPD, VCCPGM, etc on the same FPGA with the same power plane on the board.
When deriving decoupling capacitors for multiple FPGAs sharing the same power plane, each FPGA should be analyzed separately using the PDN tool. For each FPGA design, combine the required power rails as described in the "Derive Decoupling in the Power-Sharing Scenarios" section and analyze the decoupling scheme as if the FPGA was the only device on the power rail. Then repeat for each of the remaining FPGAs on the board.
High frequency decoupling capacitors are meant to provide the current needed for AC transitions and must be placed in a close proximity to the FPGA power pins. Thus the PDN tool should be used to derive the required decoupling capacitors for the unique power requirements for each FPGA on the board. For more information on the effective decoupling radius, refer to TB092: High-Speed Board Advisor Power Distribution Network (PDF).
The power regulators must be able to supply the total combined current requirements for each load on the supply, but the decoupling capacitor selections should be analyzed on a single FPGA basis.