Article ID: 000078318 Content Type: Troubleshooting Last Reviewed: 12/30/2015

DisplayPort Arria V and Stratix V Design Examples Generate Cyclone V GXB Reset

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

The Arria V and Stratix V design examples in the DisplayPort IP core incorrectly generate the Transceiver Reset IP core in Cyclone V device. This issue does not affect the design.

Resolution

To work around this issue, edit the device family name in the gxb_reset.v file and regenerate the Transceiver Reset IP core.

This issue will be fixed in version 15.1 Update 1 of the DisplayPort IP core.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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