Yes you can still perform Boundary Scan testing and / or use the SignalTap® II logic analyzer to analyze functional data within the FPGA. However, JTAG configuration is not possible after the security key has been programmed into the Stratix® II FPGA.
When using the SignalTap II logic analyzer, you must first configure the device with an encrypted configuration file using Passive Serial (PS), Fast Passive Parallel (FPP) or Active Serial (AS) configuration modes. The design must contain at least one instance of the SignalTap II logic analyzer. Once the FPGA is configured with a SignalTap II logic analyzer instance in the design, then when you open the SignalTap II logic analyzer window/GUI in the Quartus® II software, you simply need to scan the chain and it will be ready to acquire data over JTAG.