Article ID: 000078306 Content Type: Troubleshooting Last Reviewed: 11/03/2014

Why do I see timing constraint problems with the tx_clkout and pipe_hclk output clocks in Arria 10 PIPE designs?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description The tx_clkout and pipe_hclk output clocks are incorrectly constrained in the PIPE designs in the Quartus® II Software version 14.0 Arria® 10 Edition.
    Resolution

    To fix this problem, in your top level Synopsys Design Constraints (.SDC) file, follow these steps:

    1. Include the derive_pll_clock constraint in your SDC file.
    2. In a line beneath the derive_pll_clock constraint, use the remove_clock constraint to remove tx_clkout and pipe_hclk.
    3. Recreate these clocks at their interfaces using the create_clock SDC command

    This is scheduled to be fixed in a future version of the Quartus II software. 

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 SX SoC FPGA
    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA