No, the on-chip biasing network of the REFCLK input pin is disabled before and during device configuration in the Altera® transceiver based products such as Stratix® II GX, Stratix IV GX, and Arria® GX devices.
In cases where REFCLK is AC coupled, the absolute Vmin of the REFCLK input could be exceeded if the signal applied is greater than twice the magnitude of the absolute Vmin specification. This should be avoided. For example, if the device absolute Vmin is -300mV, then the differential voltage of the signal driver should not exceed 600mV.
To avoid this scenario, Altera recommends one of the following three options:
- Choose a clock driver with a differential output voltage that does not exceed twice the magnitude of the absolute Vmin limit.
- Attenuate the signal if the differential output voltage of the clock driver is greater than twice the magnitude of the absolute Vmin limit.
- Disable the clock driver until after the FPGA has configured.