Article ID: 000078259 Content Type: Troubleshooting Last Reviewed: 08/12/2012

Which voltage supply is used for single ended clock input pins in Stratix V, Arria V, and Cyclone V devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description When configured with a single ended I/O standard, the clock input pins in Stratix® V, Arria® V, and Cyclone® V devices are powered by the VCCIO supply of their respective I/O bank.
Resolution

 

Related Products

This article applies to 12 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Stratix® V E FPGA

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