Article ID: 000078242 Content Type: Troubleshooting Last Reviewed: 12/05/2024

Why does my Stratix® 10 device L-Tile or H-Tile transceiver PHY RTL simulation hang in the reset state?

Environment

    Intel® Quartus® Prime Pro Edition
    L-Tile H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP
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Description

Your Stratix® 10 device L-Tile or H-Tile transceiver PHY RTL simulation may hang in the reset state if you have not applied a Power On Reset (POR) pulse to the reconfig_reset signal of the Avalon Memory Mapped (AVMM) reconfiguration interface.

Resolution

To work around this problem, you can apply a two reconfig_clk cycle pulse to the reconfig_reset signal at the start of your RTL simulation.

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This article applies to 1 products

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