Article ID: 000078240 Content Type: Troubleshooting Last Reviewed: 03/16/2021

Why can't the E-Tile perform dynamic reconfiguration from low rate to high rates, when design starts at a low rate?

Environment

  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 DX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Transceiver PHY
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the E-Tile Transceiver Native PHY IP, dynamic reconfiguration from low rate to high rate fails, when the design is started at a low rate.

    For example, it does not allow dynamic reconfiguration from, 2.4Gbps PMA-direct (20-bit, 122 MHz transfer speed) to the higher data rate of 24.3G with PCS and FEC (32-bit, 760 MHz transfer speed).

    Resolution

    For Intel® Quartus® Prime Pro Edition version 20.4 and earlier, designs need to start at the high rate first and then dynamically reconfigure to any rate.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

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