Why can't the E-Tile perform dynamic reconfiguration from a low data rate to a high data rate, when the design starts at a low data rate?

Due to a problem with the E-Tile Transceiver Native PHY IP, dynamic reconfiguration from a low data rate to a high data rate fails, when the design is started at a low data rate.

For example, it does not allow dynamic reconfiguration from 2.4576 Gbps PMA-direct (20-bit, 122.88 MHz transfer speed) to the higher data rate of 24.33024 Gbps with PCS and FEC (32-bit, 760.32 MHz transfer speed).

For the Intel® Quartus® Prime Pro Edition Software version 20.4 and earlier, designs need to start at a high rate first and then dynamically reconfigure to any rate.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.2.