Due to a problem in the Quartus® II software versions 11.1 SP2 and earlier, the derive_pll_clocks command may generate incorrect output clock frequencies for Stratix® V PLL output clocks. To determine whether your design is affected by this problem, check whether the correct clock frequencies are displayed for the PLL output clocks in the Report Clocks panel in the TimeQuest timing analyzer.
To work around this problem, add create_generated_clock constraints to your Synopsys Design Constraints (.sdc) file to generate the correct frequencies for any PLL output clocks that are mishandled by the derive_pll_clocks command. These additional create_generated_clock constraints should appear before any derive_pll_clocks command in your .sdc files.
This problem will be fixed in a future version of the Quartus II software.