Article ID: 000078178 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any known issues with the LVDS output operation in Cyclone II devices in Quartus II software?



Yes, in Quartus® II software version 7.2 and all service pack updates, the Cyclone® II device LVDS output buffers are not properly balanced. This results in a mis-match in the level transitions between the positive pin and the negative pin.  This may place the signal crossing point above or below the typical common mode voltage level. 

To fix this imbalance, add the following assignment to the project Quartus II Settings File (QSF) for each output pin in your project that uses the LVDS standard:

set_instance_assignment -name STRATIXII_OUTPUT_DUTY_CYCLE_CONTROL OFF -to [pin name]

Although this assignment name uses Stratix® II devices, the functionality of the assignment applies to Cyclone II devices as well.  This assignment should only be made to the positive pins of the LVDS outputs.  You will need to recompile your project after saving these assignments in your project QSF.

This issue is scheduled to be fixed in the next release of the Quartus II software.

Related Products

This article applies to 1 products

Cyclone® II FPGA



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