Article ID: 000078174 Content Type: Troubleshooting Last Reviewed: 10/13/2014

Why does connecting HPS peripheral clocks to external pins via FPGA logic cause Quartus fitter errors?


  • Quartus® II Subscription Edition
  • Clock

    The following HPS Peripheral Clocks can be routed to the FPGA logic:

    • emac0_md_clk
    • emac0_gtx_clk
    • emac1_md_clk
    • emac1_gtx_clk
    • qspi_sclk_out
    • spim0_sclk_out
    • spim1_sclk_out
    • i2c0_clk
    • i2c1_clk
    • i2c2_clk
    • i2c3_clk

    Due to a problem in the Quartus® II software versions 13.0 and later, if these clocks are connected to external FPGA pin directly, quartus fit may generate an error message. The following is an example for the spim1_sclk_out signal connected to an external pin:


    Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 auto-promoted clock driver(s))
     Error (175020): Illegal constraint of auto-promoted clock driver that is part of Arria V/Cyclone V Hard Processor System ghrd_hps_0 to the region (92, 67) to (183, 137): no valid locations in region
      Info (14596): Information about the failing component:
       Info (175028): The auto-promoted clock driver name: ghrd:soc_inst|ghrd_hps_0:hps_0|ghrd_hps_0_fpga_interfaces:fpga_interfaces|spim1_sclk_out[0]~CLKENA


    More information on these clocks can be found in the "Peripheral FPGA Clocks" section of the Cyclone V or Arria® V Device Handbook, Volume 3: Hard Processor System Technical Reference Manual (, page 27-12). 


    To avoid these error messages, the clock signal must first be routed through a LUT.  This can be achieved by instantiating a lcell_comb primitive appropriate for your device family.  The following shows an example lcell_comb Verilog instantiation for the Arria V SoC spim1_sclk_out clock:


      arriav_lcell_comb wirelut( .dataa(spim1_sclk_from_hps), .combout(spim1_sclk_to_pin) );
      defparam wirelut.lut_mask = 64\'hAAAAAAAAAAAAAAAA ;
      defparam wirelut.dont_touch = "on";

    In the above example, the spim1_sclk_from_hps signal is connected to the spim1_sclk_out output port from the HPS instance.  The spim1_sclk_to_pin signal can be connected to the top level output port and assigned to an FPGA pin.


    The use of a lcell_comb primitive will minimize resources.  Using a small inferred Boolean combinational function will also avoid this error.  Using the Boolean function will avoid having to instantiate a primitive, but may result in slightly higher resource usage.   The following is example Verilog code showing an inferred Boolean that also avoids an error by ANDing the clock with an active low reset signal (causing an inferred LUT instance):

      assign spim1_sclk_to_pin = spim1_sclk_from_hps & resetn;

    This problem is scheduled to be fixed in a future release of the Quartus II software.

    Related Products

    This article applies to 5 products

    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA



    All postings and use of the content on this site are subject to Terms of Use.