Article ID: 000078172 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does my fractional PLL with the reconfiguration feature enabled fail to lock in Stratix V devices?

Environment

    Quartus® II Subscription Edition
    PLL
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Description

Due to a problem in Quartus® II versions 11.1SP2 and earlier, fractional PLLs implemented with the Altera® PLL IP and attached Altera PLL reconfig IP may fail to lock when implemented in certain locations on Stratix® V devices. 

An additional symptom is that the mgmt_waitrequest signal is always asserted.

Resolution

If PLLs with reconfiguration are used on Stratix V devices, use version 12.0 or later of the Quartus II software.

Related Products

This article applies to 4 products

Stratix® V GX FPGA
Stratix® V GT FPGA
Stratix® V E FPGA
Stratix® V GS FPGA

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