Article ID: 000078157 Content Type: Troubleshooting Last Reviewed: 07/28/2015

Why does the Modular Scatter-Gather DMA IP fail to generate when using VHDL in Qsys?

Environment

    Quartus® II Subscription Edition
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Description Due to a problem in the Quartus® II software version 14.1, the Modular Scatter-Gather DMA (MSGDMA) IP will fail during generation of the simulation model when the simulation language is set to VHDL.
Resolution

This problem is fixed starting with the Quartus II software version 15.0.

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