Description
Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this Internal Error in your Arria® V, Cyclone® V or Stratix® V design. This error occurs if your design contains a Transceiver Native PHY configured to use an external TX PLL and the xN clock network.
Resolution
To work around this problem, do not enable the option Use external TX PLL when also using the xN line clock network.
Future versions of the Quartus II software are scheduled to generate an error message for this configuration.