Critical Issue
Description
This problem affects DDR3 and DDR4 interfaces using the Ping Pong PHY feature on Arria 10 devices.
Setup timing violations for transfers from the secondary hard memory controller to core logic may occur in interfaces using the Instantiate two controllers sharing a Ping-Pong PHY option, at memory clock frequencies faster than 1067MHz.
Resolution
The workaround for this issue is to specify a slower memory clock frequency.
This issue is fixed in version 15.1.