Rate Governing Deviation From Target Average For 1- and 2-Lane DispayPort Configurations Operating In MST Mode

Because the Symbol Sequences are 4-symbol multiples, the Stream Symbols rate throttling is affected when the DisplayPort TX core operates in Multi-Stream Transport (MST) mode and the actual requested lane count is 1 or 2.

For example, for a 2-lane configuration:

TARGET_Average_StreamSymbolPerMTP = 8.5

Average_StreamSymbolTimeSlotsPerMTP = 9

FRAC(TARGET_Average_StreamSymbolPerMTP) = 0.5

TAVG_TSx (Source MST Registers at address 0x00aa for Stream x) = CEIL (FRAC (8.5) * 64) = CEIL 0.5) * 64 = 32

The ratio of 32/64 or 1/2 means the rate governor within the core will request for Virtual Channel Payload Fill (VCPF) insertion every other Multi-Stream Transport Packet (MTP).

For a 4-lane configuration, the number of Stream Symbol time slots per MTP fluctuates between 8 and 9.

For a 2-lane configuration, if the VCPF insertion rate is 1/2, the number of Stream Symbol time slots per MTP fluctuates between 7 and 9. This means over every 4 MTPs, the Stream Symbols only add up to 32 (7 9 7 9) instead of the expected 34 (8.5 *4). For every 4 MTPs, there will be 2 Stream Symbols span to the next MTP.

Similarly for a 1-lane configuration, if the VCPF insertion rate is still 1/2, the number of Stream Symbol time slots per MTP fluctuates between 5 and 9. This means over every 8 MTPs per lane, the total Stream Symbols is only 56 (5 9 5 9 5 9 5 9) instead of the expected 68 (8.5 * 8). For every 8 MTPs, there will be 12 Stream Symbols span to the next MTP.

This issue will eventually cause the stream bandwidth to exceed the link bandwidth.

To work around this issue, you can dynamically program the TAVG_TSx register at address 0x00aa based on the equation below:

TAVG_TSx = CEIL ( ( 1- (1 - FRAC (TARGET_Average_StreamSymbolPerMTP) ) * actual lane count / 4) * 64

This equation ensures the proper rate throttling.

Note: This equation does not work when FRAC(TARGET_Average_StreamSymbolPerMTP) = 0.

Using this equation, you should get the following VCPF insertion rate across actual lane count configuration:

• 4-lane: request to insert VCPF once every 2 MTPs
• 2-lane: request to insert VCPF once every 4 MTPs
• 1-lane: request to insert VCPF once every 8 MTPs

For example, for a 0.5 fraction, the expected TAVG_TSx is:

• 4-lane: TAVG_TSx = CEIL ( ( 1 - 0.5 ) * 4 / 4 ) * 64 ) = CEIL ( ( 1 - 0.5 ) * 64 ) = 32

32 means ratio of 32/64 or 1/2 which means the rate governor request to insert VCPF once every 2 MTPs.

• 2-lane: TAVG_TSx = CEIL ( ( 1 - 0.5 ) * 2 / 4 ) * 64 ) = CEIL ( ( 1 - 0.25 ) * 64 ) = 48

48 means ratio of 48/64 or 3/4 which means the rate governor request to insert VCPF once every 4 MTPs.

• 1-lane: TAVG_TSx = CEIL ( ( 1 - 0.5 ) * 1 / 4 ) * 64 ) = CEIL ( ( 1 - 0.125 ) * 64 ) = 56

56 means ratio of 56/64 or 7/8 which means the rate governor request to insert VCPF once every 8 MTPs.

This issue is fixed in version 16.1 of the DisplayPort IP core.