Description
You may get this error when simulating a Verilog HDL output file from the MAX PLUS® II software in Viewlogic's VCS simulator because the Verilog HDL directives used in the MAX PLUS II software are compatible with the Cadence Verilog HDL directives but may not be compatible with all EDA tool vendors' Verilog HDL directives.
To correct this error, locate the veriuser.c and Convert_hex2ver.o files included with the Cadence Verilog-XL simulator interface provided with the MAX PLUS II software for UNIX workstations. The default installation location for these files is the /usr/maxplus2/cadence/verilog directory. Compile the veriuser.c file through a programmable language interface (PLI) and copy the compiled veriuser.c and the Convert_hex2ver.o files into your simulation directory.