Article ID: 000078110 Content Type: Troubleshooting Last Reviewed: 01/08/2015

Why do I experience slow Fmax for Nios II system in Arria V (non GZ family)?

Environment

  • Quartus® II Subscription Edition
  • Nios® II Processor
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When user selects "DSP Block" implementation as the Hardware multiplication type for Nios® II, users may observe slower Fmax performance in Nios II system. This is because Arria® V (non GZ) family does not supports 32-bit multiplication in its hard multiplier logic which results in additional LEs being instantiated. The hard multiplier together with the additional LEs will create critical path in Nios II.

    Resolution

    Users can switch to "Logic Elements" implementation or "None" as the Hardware multiplication type for Nios II if the application code does not need multiply instruction.

    Related Products

    This article applies to 5 products

    Arria® V GT FPGA
    Arria® V FPGAs and SoC FPGAs
    Arria® V GX FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA

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