Article ID: 000078100 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why is the column address strobe (CAS) and address bus at undefined value in the user mode when I try to simulate DDR2 High Performance controller?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You have to initialize the following signals going to the controller from the example driver:

local_address, local_be, local_cs_addr, local_read_req, local_row_addr, local_size, local_wdata.

Failing to initialize these signals when designing the user logic will cause the issue of undefined CAS value, this might also cause the local_write_req and local_wdata_req signals to go high at the same time and might cause other unintended controller behavior.





                                                                                                                        
                                                                                          local_write_req,

Related Products

This article applies to 3 products

Stratix® II FPGAs
Stratix® III FPGAs
Cyclone® III FPGAs