Article ID: 000078093 Content Type: Troubleshooting Last Reviewed: 07/09/2014

Why doesn't the clock frequency shown in Table 1-9. Recommended Device Family Speed Grades of the IP Compiler for PCI Express User Guide match the clock frequency shown in the IP GUI?

Environment

    PCI Express
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The clock frequency shown in Table 1-9. Recommended Device Family Speed Grades of the IP Compiler for PCI Express® User Guide does not match the clock frequency shown in the IP GUI, as the table details the IP Internal Clock Frequency, while the IP GUI details the user side Application clock frequency.

Related Products

This article applies to 10 products

Cyclone® IV GX FPGA
Cyclone® II FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Arria® II GZ FPGA
Stratix® III FPGAs
Stratix® IV GX FPGA
Arria® II GX FPGA
Cyclone® III FPGAs
Stratix® IV E FPGA

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