Article ID: 000078091 Content Type: Troubleshooting Last Reviewed: 10/09/2013

Why is the PCI Express Hard IP not generating ECRC when Advanced error reporting (AER), ECRC checking, ECRC generation and ECRC forwarding are enabled?

Environment

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Description

The PCI® Express Hard IP will not automatically set the TLP TD bit if ECRC forwarding is enabled. When ECRC forwarding is enabled the TLP TD bit will be sent unchanged by the IP.  You should ensure that the Avalon Streaming (Avalon-ST) header has the TD bit set.


If ECRC forwarding is not enabled and ECRC generation is enabled, the core will automatically set the TLP TD bit and generate the ECRC.

Resolution To automatically set the TLP TD bit in the transmitted header, disable the ECRC forwarding.

Related Products

This article applies to 16 products

Cyclone® V SX SoC FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® IV GX FPGA
Stratix® V GT FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Stratix® IV GX FPGA
Arria® II GX FPGA
Stratix® IV GT FPGA

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