Article ID: 000078082 Content Type: Troubleshooting Last Reviewed: 08/28/2013

Why does my 10G RD implementation show different behavior at reset at different times?



If you are experiencing unreliable behavior with the 10G Ethernet Reference Design please review design clocking and reset which are the normal causes of poor performance. The clocking schemes for the 10G Ethernet functional blocks have been provided as the following:

1.1 MAC PHY Core Clocks & Resets

In this scenario, the PHY provides a clock (coreclock_out) that can be used for MAC and MAC side of the FIFO logic.

Figure 1

1.2 MAC Only Core Clocks and Resets

In this scenario the client/user logic provides clock for the MAC and MAC side of the FIFO logic. The reset connections are shown in MAC-PHY case above are omitted in the following diagrams for clarity.

Figure 2

1.3 MAC XGMII Core Clocks & Resets

In this scenario the client/user PLL provides (system) clock for the MAC, MAC side of the FIFO logic, and the XGMII transmit data and clock interface.



Figure 3


1.4 Reset Synchronization

Based on the core generated, all the individual resets must be synchronized with their respective clocks. An example of reset synchronization for MAC XAUI core has been provided in the following diagram.


Figure 4

Related Products

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Stratix® IV GX FPGA



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