Article ID: 000078068 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What would cause all of the outputs on my FPGA to suddenly tri-state during user mode?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Having the DEV_OE pin enabled in the Quartus® II software for your project, but not connected or floating on the board may cause all of the I/O pins to tri-state during user mode.

When asserted, the DEV_OE pin will override all tri-state controls on the device and force all I/O pins to be tri-stated.  If the DEV_OE pin is unconnected on the board but is enabled in the Quartus II software, the floating voltage on the unconnected pin will be unknown and can enable or disable the feature.  Variance in the temperature, voltage, or device process, as well as noise on the board can cause the voltage on the floating pin to drop low enough to de-assert the DEV_OE pin which will then tri-state all of the I/O pins in the device.

If all of the outputs unexpectedly tri-state during user mode, check to see if the DEV_OE pin is floating on the board, and if the pin has been enabled for your project in the Quartus II software.

Use the following steps to disable the DEV_OE pin in the Quartus II software:

  1. Go to Assignments => Device
  2. Click on Device & Pin Options...
  3. Select the General Category
  4. Turn off the Enable device-wide output enable (DEV_OE) option

The QSF (Quartus II Settings File) variable for this option is ENABLE_DEVICE_WIDE_OE.

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