ODT Launches Off System Clock

In designs with a separate address and command clock, the ODT output launches from the system clock, not from this address and command clock.

This issue affects the following configurations:

• DDR2 SDRAM controller (not DDR SDRAM)
• ODT is turned on
• CAS latency is set to three
• The design uses a separate address and command clock and not the default system clock

This issue has no design impact.

Use a CAS latency of four, which means one extra cycle of read latency, or use the DDR2 SDRAM High-Performance controller, which uses the ALTMEMPHY megafunction to transfer all the address and command outputs to the correct clock.

This issue will not be fixed.