Issue 57356, version 9.0
The DPA PLL Calibration section has separate references to Arria® II GX and Arria II GZ devices. All information related to DPA PLL calibration is applicable to both variants of the Arria II device family. The individual references to "Arria II GX" and "Arria II GZ" devices will simply be replaced with "Arria II" devices in a future version of the document
Issue 388158, version 8.0
Table 2-2 has a typo in the description for Register Outputs. The bold text "Source Multiply" should instead say "Source Multicycle".
The description for Register Outputs is incomplete. The following describes the Register Outputs option:
When this option is on, the outputs of the receiver are registered by the rx_outclock signal in non-DPA mode and in DPA mode. The outputs of the receiver are registered by the rx_divfwdclk signal in Soft-CDR mode.
Turn off this option if you do not want to register the receiver outputs with auto-generated registers. In this mode, you must register the receiver outputs in your design logic. For Stratix® II and Arria® GX devices, you must also specify a Source Multicycle assignment from the receiver to the output registers with a value equal to the deserialization factor. For other families, these assignments are auto-generated.