Article ID: 000078049 Content Type: Error Messages Last Reviewed: 08/13/2012

Error: Can't fit fan-out of node <your pll output> into a single clock region

Environment

    Clock
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see this error, in the Quartus® II software, during the fitter stage if you cascade a GPLL to a MPLL in your Cyclone® IV GX design.

The Quartus II software may incorrectly auto-place your cascaded MPLL in locations PLL_6 or PLL_7. These two PLL locations only support upstream PLL cascading.

To ensure that your MPLL is correctly placed to support downstream cascading use a PLL location assignment to assign the required MPLL location to either PLL_5 or PLL_8.

 

Related Products

This article applies to 1 products

Cyclone® IV GX FPGA

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