Article ID: 000078048 Content Type: Troubleshooting Last Reviewed: 09/05/2013

What is the maximum specification of the phasedone low time?

Environment

  • PLL
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The maximum phasedone low pulse width is 3 scanclk cycles.

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    This article applies to 1 products

    Stratix® III FPGAs

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