Article ID: 000078045 Content Type: Product Information & Documentation Last Reviewed: 09/12/2012

How do I ensure consistent behavior between Avalon-MM and Avalon-ST PCIE HIP in the Stratix V device family?

Environment

    Quartus® II Subscription Edition
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Description

For the Stratix® V device family, to ensure consistent behavior between the Avalon®-MM and Avalon-ST PCI Express® Hard IP, 3 parameters need to be changed from the Avalon-MM wrapper to match the default values in the Avalon-ST wrapper.

Resolution

In the file altpcie_sv_hip_avmm_hwtcl.v, look for the following parameter definitions near the top of the file (around line 37 and 148) and make the changes identified:

   parameter deskew_comma_hwtcl         =  "skp_eieos_deskw",
   parameter rx_cdc_almost_full_hwtcl   =  6,
   parameter tx_cdc_almost_full_hwtcl   =  6,

Change to:

   parameter deskew_comma_hwtcl         =  "com_deskw",
   parameter rx_cdc_almost_full_hwtcl   =  12,
   parameter tx_cdc_almost_full_hwtcl   =  11,

Related Products

This article applies to 2 products

Stratix® V GT FPGA
Stratix® V GX FPGA

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