Article ID: 000077988 Content Type: Troubleshooting Last Reviewed: 12/15/2014

Synthesis fails with "Error (10170): Verilog HDL syntax error..." for designs using debug instrumentation to the Qsys interconnect

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

In the Quartus II software release version 14.1, synthesis fails for designs using Qsys interconnect instrumentation. The Quartus II software will display an error similar to the following:

Error (10170): Verilog HDL syntax error at <qsys system name>_mm_interconnect_0_monitor_m_0_master_gatherer.sv(423) near text "-"
Resolution

You must use the Quartus II software release version 13.1 or 14.0 if using debug instrumentation to the Qsys interconnect. This issue will be fixed in a future software release.

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This article applies to 1 products

Intel® Programmable Devices

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