Critical Issue
When you configure the DisplayPort TX core to any configurations that enable the pixel clock to run faster than the TX link clock by at least a factor of 6, the image may not display on the monitor.
This issue is caused by the periodical overflow in the DCFIFO that crosses the video data from pixel clock to link clock domain. For example, this issue will occur if you configure the TX core to 1 pixel per clock and 4 symbols per clock at RBR (1.62 Gbps) with 4 lanes to transmit 1856x1392@75 Hz at 18 bpp. In this particular case, the pixel clock is 288 MHz and the link clock is 40.5 MHz. The DCFIFO will overflow and you will not see the image output.
To work around this issue, change the pixels per clock, symbols per clock, link rate, and lane count configurations to lower the ratio of pixel clock to TX link clock. For example, to transmit 1856x1392@75Hz at 18bpp, you can use 1 pixel per clock, 4 symbols per clock, HBR (2.7 Gbps) with 2 lanes so that the pixel clock is 288 MHz and TX link clock is 67.5 MHz.
This issue is fixed in version 16.0 of the DisplayPort IP core.