Why doesn't my output clock toggle when simulating cascaded PLL output counters in Cyclone III or Cyclone IV devices?

Due to a problem in the Quartus II software version 9.1 and later, output clocks may not toggle during functional simulation of PLL output counter cascading in designs targeting Cyclone III and Cyclone IV devices. This problem is related to the functional simulation model and does not affect hardware behavior.

To work around this problem, use timing simulation when the ALTPLL megafunction is configured to use output counter cascading. Timing simulation is not affected by the problem in the functional simulation models.