Article ID: 000077934 Content Type: Troubleshooting Last Reviewed: 08/20/2015

Can I drive more than one transceiver reference clock input from an fPLL via the cascade clock network on Cyclone V GX devices?

Environment

  • Cyclone® V GT FPGA
  • Cyclone® V SX SoC FPGA
  • Cyclone® V GX FPGA
  • Cyclone® V ST SoC FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    No, each fPLL can only drive a single refclk input on the cascade clock network of Cyclone® V GX devices.

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