JESD204B IP Core Testbench (ip_sim) Errors for Variants with L>6

For bonded mode variants with Lanes per converter device (L) greater than 6, you will encounter the following error when generating the simulation files:

For non-bonded mode variants with L>6, you may encounter a simulation failure.

The existing IP core testbench implements PLL feedback compensation bonding configuration for bonded mode, and x1 bonding configuration for non-bonded mode. You must regenerate the ATX PLL from the IP Catalog and change the bonding configuration to x6/xN bonding for bonded mode, or xN bonding for non-bonded mode.

This issue affects the JESD204B IP core testbench targeting an Arria 10 device.

Generate the Arria 10 Transceiver ATX PLL from the IP Catalog with the following parameter settings:

Bandwidth: medium

PLL output frequency: <data rate>/2

PLL integer reference clock frequency: <data rate>/20 (for Hard PCS), <data rate>/40 (for Soft PCS)

Select Include Master Clock Generation Block

For bonded mode, select Enable bonding clock output ports, PMA interface width = 20 (for Hard PCS) or PMA interface width = 40 (for Soft PCS)

For non-bonded mode, select Enable x6/xN non-bonded high-speed clock output port

For details on bonding mode implementation, refer to the Arria 10 Transceiver PHY User Guide, "Implementing x6/xN Bonding Mode" and "Implementing Multi-Channel xN Non-Bonded Configuration" topics.

This issue will be fixed in a future release.