Critical Issue
Description
CPRI IP core variations that generate in VHDL and that target a 28-nm device cannot simulate successfully in the Aldec Riviera-PRO simulator.
The simulator displays the following error message:
ELAB2: Fatal Error: ELAB2_0103 Input and inout ports
of type reg are not allowed in Verilog modules instantiated in VHDL.
Resolution
Use a different simulator to simulate your CPRI IP core VHDL variation that targets a 28-nm device.
This issue is fixed in version 13.0 of the Quartus II software.