Warning (10631): VHDL Process Statement warning at <filename>.vhd(): inferring latch(es) for signal or variable "<name>", which holds its previous value in one or more paths through the process

Due to a problem in the Quartus® II software, you may see this warning if your code implements an incrementer or decrementer with an asynchronous reset where some of the bits remain constant.  For example, with the following code, the Quartus II software will erroneously report a warning for the lower bits:

process (reset, clk)
begin
 if reset = '1' then
  minus_8_count_int <= TO_UNSIGNED(16,5);
 elsif (rising_edge(clk)) then
  minus_8_count_int <= minus_8_count_int - 8;
 end if;
end process;

As the counter decrements by 8, the lower 3 bits are unused and before they get optimized away, the Quartus II Integrated Synthesis warns that they are latches.

It is safe to ignore the warning in this case as no latches are implemented.