Article ID: 000077893 Content Type: Troubleshooting Last Reviewed: 03/23/2022

Why does my F-Tile PMA/FEC Direct PHY Intel FPGA IP Soft CSR register readback value for PMA Type (FGT/FHT) and RX CDR lock-to-data status is invalid using the Intel® Quartus® Prime Pro Edition Software versions 21.2 ?


  • Intel® Quartus® Prime Pro Edition

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2, the F-Tile PMA/FEC Direct PHY Intel FPGA IP Soft CSR register has an invalid readback value.

    If the user performs a readback value of the following register address below:

    1)  PMA Type

    a.   Register name: PMA_type

    b.   Value:

    0: FGT

    1: FHT

    c.   Offset address: 0x800[12]

    d.   Problem observed: The PMA_type readback value might not be correct.

    2)  RX CDR Locked-to-data

    a.  Register name: rx_cdr_locked2data

    b.  Value:

    0: RX CDR PLL is unlocked.

    1: Corresponding physical lane RX CDR is locked to data.

    c.   Offset address: 0x814[15:0]

    d.   Problem observed: The RX CDR readback value for locked-to-data status is always stuck at ‘0’, even though the RX channel(s) has achieved locked-to-data mode.               

    You will readback an invalid value for the above two mentioned registers. This problem is valid for both PMA Direct and FEC Direct mode.


    A patch is available to fix this problem for the Intel Quartus Prime Pro Edition Software version 21.2. Download and install Patch 0.16 from the appropriate link below.

    Download patch 0.16 for Windows (quartus-21.2-0.16-windows.exe)
    Download patch 0.16 for Linux (
    Download the Readme for patch 0.16 (quartus-21.2-0.16-readme.txt)

    The patch updates Soft CSR register value to provide a correct readback value for both the mentioned registers.
    After the workaround/fix is implemented:

    1)  PMA Type

    The PMA Type readback value for FGT type is ‘0’ and FHT is ‘1’.

    2)  RX CDR Locked-to-data

    The RX CDR locked-to-data readback value reflects the actual status of the channel, i.e asserted when the RX channel(s) achieve LTD and de-asserted when LTD is not achieved.

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series
    Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series



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