Due to a problem in the Quartus® II software versions 11.1 SP2 and earlier, you may see incorrect minimum pulse width violations for M20K memory blocks in Stratix® V I2 speedgrade devices when performing timing analysis using the fast timing model. This problem is due to an incorrect timing model for Stratix V I2 speedgrade devices.
Refer to Table 2-27 of the DC and Switching Characteristics for Stratix V Devices (PDF) chapter of the Stratix V device handbook for details on the Memory Block Performance Specifications for Stratix V Devices.
If you are operating the memories within the specification, the minimumum pulsewidth violations can be safely ignored.
This problem is fixed beginning with the Quartus II software version 12.0.