Article ID: 000077887 Content Type: Troubleshooting Last Reviewed: 08/13/2012

When should I use the cal_blk_powerdown signal to calibrate the transceiver on-chip termination?

Environment

  • Stratix® IV GT FPGA
  • Stratix® IV GX FPGA
  • Stratix® II GX FPGA
  • Arria® GX FPGA
  • Arria® II GZ FPGA
  • Arria® II GX FPGA
  • Stratix® V GX FPGA
  • Cyclone® IV GX FPGA
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Description

Transceiver on-chip termination calibration should only need to take place once at device power up. However, if your channel has marginal signal integrity, and your device operates at device temperature extremes, then recalibration of the transceiver on-chip termination by pulsing the cal_blk_powerdown signal might provide more margin.

Example: If your device was powered up and initially calibrated at Tj(min), and your channel has marginal signal integrity, but normal operating temperature is close to Tj(max) then recalibrating on-chip termination at Tj(max) might improve signal integrity margins.

Bit errors may be seen during on-chip termination recalibration.

Note: During the design phase, you must ensure through signal integrity simulation that your channel offers sufficient margin for the full temperature range of your design.

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