Article ID: 000077842 Content Type: Troubleshooting Last Reviewed: 06/29/2014

Why does my Stratix V GX ES Device, Native PHY design show the following error: 10G RX PCS param 'hd_pcs10g_rx_chnl_frmsync_mfrm_length' set to illegal 'mfrm_user_length'?

Environment

  • Stratix® V GX FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Native PHY does not support the use of the 10G PCS on Stratix® V GX ES devices. To work around this issue you should use the Low Latency PHY or compile for a production Stratix V GX device?

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