Why is the PCI Express core clock out incorrectly set to 125MHz in SOPC Builder when an application clock of 62.5MHz was specified in the IP?

Due to a bug in SOPC® Builder, the PCI Express® Core Clock Out is always being set to 125MHz.

This can cause timing failures in -7 and -8 device speed grades.

To workaround this issue:

Manually edit the file pcie_compiler_0_core.v and change
altpcie_hip_pipen1b_inst.core_clk_divider = 2 to
altpcie_hip_pipen1b_inst.core_clk_divider = 4

This issue effects all versions of SOPC Builder up to and including v10.1.

This issue has been fixed in Quartus® II version 10.1SP1. Customers are advised to upgrade to this release of Quartus II and regenerate.