Article ID: 000077821 Content Type: Troubleshooting Last Reviewed: 01/01/2015

What guidelines should I follow when capturing a schematic with Altera FPGAs?

Environment

  • Stratix® III FPGAs
  • Stratix® II FPGAs
  • Stratix® II GX FPGA
  • Cyclone® III FPGAs
  • Arria® GX FPGA
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Description

When capturing a schematic with Altera® FPGAs, you can use the Pin Connection Guidelines (PCGs) to understand the board level connection of the device you are using. Currently, PCGs are available for the following Altera devices:  Stratix® IV, Stratix III, Stratix II GX (which can also be used for Stratix II devices excluding the transceiver portion), Cyclone® III, Arria® II GX, and Arria GX.

The PCGs are also a useful tool for schematic reviews and pinout reviews of your design.

These guidelines are found in the Literature Page under Pin Connection Guidelines. A link to the PCGs is also found in the Device Pinouts page for the supported device families.

You can also find PCGs for the Altera FPGAs by performing a search for "PCG".

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