RapidIO II IP Core I/O Logical Layer Master Port Does Not Deassert Write Request Signal After waitrequest Signal is Deasserted

The RapidIO II IP core’s I/O Logical layer master port is supposed to implement the Avalon-MM interface master protocol. However, the IP core does not implement this protocol correctly. Specifically, the iom_rd_wr_write output signal does not comply with the specification if the iom_rd_wr_waitrequest input signal is already asserted at the time the IP core initially asserts the iom_rd_wr_write output signal. In this case, the IP core does not deassert this signal even after the iom_rd_wr_waitrequest input signal is deasserted.

According to the Avalon-MM protocol specification, the master must hold the write request signal (iom_rd_wr_write) asserted until after the slave deasserts the iom_rd_wr_waitrequest signal, and then deassert the write request after the write is completed. However, with the current IP core implementation, the IP core maintains the write request asserted even after the write is completed. In this case the IP core never deasserts the write request signal (iom_rd_wr_write). As a result, the Avalon-MM slave will erroneously assume that the IP core is making additional, new write requests.

For more information about the Avalon-MM specification, refer to Avalon Interface Specifications.

This issue has no workaround.

This issue is fixed in version 14.1 of the RapidIO II IP core.