There is a problem in the Quartus® II software version 8.1 that could cause VHDL tri-state signals to be inferred incorrectly as multiplexers. If the signal is connected to a device output pin, the compilation result could cause the pin to drive out to the board instead of acting as a tri-state output.
The software problem occurs only if a VHDL design entity contains an unused output port with a default value that includes 'Z' (that is, the output port has the 'Z' tri-state assignment in the entity declaration but no explicit assignment to the signal in the design). When the problem occurs, any inferred tri-state logic described by behavioral statements in the enclosing architecture will be incorrectly inferred as multiplexers. The problem is restricted to the single hierarchy in the architecture and not any instantiated hierarchies, unless other entities have the same type of unused output port with a default value that includes 'Z'. Refer to the example at the end of this Solution for a small design that illustrates this problem.
If the affected tri-state signals are internal tri-state connections, inferring multiplexers is expected because there is no internal tri-state logic in Altera devices. However, if tri-stated entity ports feed I/O pins on the device, this software behavior may cause the unused output pin to drive out to the board instead of acting as a tri-state output, which can cause signal contention in the system.
To work around the problem and infer the defined tri-state behavior, explicitly assign the unused output pins to a tri-state value using a signal assignment in the design, instead of relying on the default statement. For example, use a statement like unused_output <= 'Z'; or unused_output <= (others => 'Z');
A patch is available to fix this problem in the Quartus II software version 8.1. Download the Windows patch 0.34 or Linux patch 0.34, then install the patch and recompile the design.
This software problem will also be fixed in a future version of the Quartus II software.
The following is an example design that is affected by this problem:
library ieee;
use ieee.std_logic_1164.all;
entity example is
port (
en : in std_logic;
data : in std_logic;
unused_output: out std_logic := 'Z';
other_output : out std_logic);
end example;
architecture rtl of example is
begin
-- other_output should be tri-state but won't be tri-state due to this problem
other_output <= data when en = '1' else 'Z';
end rtl;
To infer the correct tri-state behavior for both output pins in the design example above with the Quartus II software version 8.1 , add the following statement in the architecture: unused_output <= 'Z';