Article ID: 000077811 Content Type: Product Information & Documentation Last Reviewed: 04/15/2014

How do I fix the core setup timing violations when I bond two DDR3 hard memory controllers from the top edge to bottom edge of the FPGA device?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When you bond two DDR3 hard memory controllers (HMC) located on the top and bottom edges and use pll_afi_half_clk as the clock for the MPFE port, you may get core setup timing violations between the bonding_in_* and bonding_out_* paths.

 

Although the MPFE clock is allowed to run up to half of the hard memory controller frequency, the maximum MPFE clock frequency depends on the core fabric performance. The path from bonding_out_* to bonding_in_* is routed through the core fabric and is too long, resulting in the timing violation.

Resolution

Lower the MPFE clock frequency to achieve timing closure and increase the data width of the MPFE port to maintain the same bandwidth on the memory interface.

Related Products

This article applies to 13 products

Cyclone® V SX SoC FPGA
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Arria® V GX FPGA
Arria® V FPGAs and SoC FPGAs
Arria® V GT FPGA
Cyclone® V FPGAs and SoC FPGAs
Cyclone® V E FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Cyclone® V SE SoC FPGA

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