Article ID: 000077804 Content Type: Troubleshooting Last Reviewed: 01/11/2016

Why can't I constrain the timing path for the HPS SPI peripheral interface when routed to the FPGA fabric?

Environment

    Intel® Quartus® Prime Pro Edition
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Description Due to a problem in the Quartus® II software version 15.0, no timing paths are available to constrain the, Altera Arria® 5 and Cyclone® V SoC  SPI interface when routed to the FPGA.
Resolution This issue is fixed in the Quartus II software from version 15.1.1.

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