Article ID: 000077798 Content Type: Troubleshooting Last Reviewed: 06/17/2023

What is the meaning of the "SerialLite II Deskew Tolerance" in Table 19 of the SerialLite II IP Core User Guide (PDF)?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Max Deskew (Cycles) in Table 19 of the SerialLite II IP Core User Guide (PDF) means the maximum lane to lane skew the transceiver is able to accept.

Resolution

For example: If the Transfer Size is 4 then the Maximum Deskew time accepted by transceiver is 2 tx_coreclock clock cycles. In contrast if the Transfer Size is 1 then the Maximum Deskew time accepted by transceiver is 14 tx_coreclock clock cycles.

Related Products

This article applies to 6 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Arria® V FPGAs and SoC FPGAs
Arria® II GX FPGA
Cyclone® V FPGAs and SoC FPGAs
Stratix® V FPGAs
Stratix® IV FPGAs

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