Article ID: 000077767 Content Type: Troubleshooting Last Reviewed: 12/08/2014

Why does the HPS SDRAM fail to calibrate on my single-core SOC FPGA?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the Quartus® II software version 13.1 and 14.0,  the DDR IO settings in the software handoff files for single-core SOC FPGAs may be incorrect leading to SDRAM calibration failures on the HPS SDRAM controller.
    Resolution

    To work around this problem follow the steps below:

    1. Make a copy of your Quartus II and Qsys Project and target the dual-core variant of the SOC FPGA you are using
    2. Compile your dual-core Quartus II project
    3. Create a new BSP based on the dual-core Quartus II project using bsp-editor, but do not run make
    4. Copy the following file from the duel-core Preloader BSP into the single-core BSP Preloader
      spl_<bsp name>/generated/Iocsr_config_cyclone5.c
    5. Clean and make your single-core Preloader:  make clean  make
    6. Optional :  Check that <Single-core BSP>/uboot-socfpga/board/altera/socfpga/iocsr_config_cyclone5.h matches the iocsr_config_cyclone5.h  file in your dual-core preloader BSP

    This problem is scheduled to be resolved in a future release of the Quartus II Software.

    Related Products

    This article applies to 5 products

    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA

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