Why do I see non-intuitive serial loopback behavior when using the Quartus® Prime Software Transceiver Toolkit with Stratix® 10 and Agilex™ 7 FPGA E-Tile devices?

You may see non-intuitive serial loopback behavior using the Quartus® Prime Software Transceiver Toolkit with Stratix® 10 and Agilex™ 7 E-Tile devices if you have not run any kind of RX Adaptation.

It is mandatory to run RX Adaptation when using Stratix 10 and Agilex™ 7 FPGA E-Tile transceivers. If you have not run RX Adaptation, you may see the following behaviors:

• The toolkit shows 0 Bit Error Rate (BER) irrespective of internal or external serial loopback
• 0 BER errors are seen when implementing internal and external loopback on your system  and switching internal serial loopback on and off without halting traffic

To work around this problem, you must always run RX Adaptation on your Stratix® 10 and Agilex™ 7 FPGA E-Tile transceivers. A flow for initializing your E-Tile transceivers in the Intel Quartus Prime Software Transceiver Toolkit is documented in the following article:

https://www.intel.com/content/www/us/en/support/programmable/articles/000077764.html