Article ID: 000077763 Content Type: Troubleshooting Last Reviewed: 07/15/2021

Why do I see non-intuitive serial loopback behaviour when using the Intel® Quartus® Prime Transceiver Toolkit with Intel Stratix® 10 and Intel Agilex® E-Tile devices?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see non-intuitive serial loopback behaviour when using the Intel Quartus Prime Transceiver Toolkit with Intel Stratix 10 and Intel Agilex E-Tile devices if you have not run any kind of RX Adaptation.

    It is mandatory to run RX Adaptation when using Intel Stratix 10 and Intel Agilex E-Tile transceivers. If you have not run RX Adaptation you may see behaviour like:

    • The toolkit showing 0 Bit Error Rate (BER) irrespective of internal or external serial loopback.
    • 0 BER errors seen when implementing internal and external loopback on your system, and switching internal serial loopback on and off without halting traffic.
    Resolution

    To work around this problem, you must always run RX Adaptation on your Intel Stratix 10 and Intel Agilex E-Tile transceivers. A flow for initializing your E-Tile transceivers in the Intel Quartus Prime Transceiver Toolkit is documented here.

    https://www.intel.com/content/www/us/en/support/programmable/articles/000077764

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