Article ID: 000077761 Content Type: Troubleshooting Last Reviewed: 09/24/2013

Why am I seeing a difference in the option of number of chip selects for DDR3 UniPHY IP generated in Quartus II V12.0 and V13.0 and later versions?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description The behaviour of DDR3 IP generated in QII V12.0 is incorrect. The number of chip select option for DDR3 UniPHY controller is limited to 2 for both Arria V and Cyclone V device.
    Resolution This issue has been fixed in QII V13.0

    Related Products

    This article applies to 3 products

    Arria® V GZ FPGA
    Arria® V GT FPGA
    Arria® V GX FPGA

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